搜索资源列表
delay_early_gate.rar
- 超前滞后锁相环，可以精确的是想符号同步的 采用V_LOG代码编写 可以直接使用,Lead and lag phase-locked loop can be accurate is to synchronize the use of symbols V_LOG code can be directly used to prepare
OFDM_16QAM
- ofdm下的QAM调制解调系统实现，包括定时同步-QAM OFDM modulation and demodulation under the system implementation, including timing synchronization
coarsefrequencyoffset
- ofdm粗频偏估计程序，包含5个模块，基于PN序列的同步-ofdm coarse frequency offset estimation procedures, including the five modules
SDHAnalysis
- 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extra
Frame_Detection
- 802.11a帧检测源码，包括帧同步，书上光盘带的源码。-802.11a frame detection source, including frame synchronization, books, CD-ROM with source code.
mobiledemo
- mobile 实现客户端数据同步的例子! （sqlce 数据库）-mobile data synchronization client implementation examples! (sqlce database)
ofdm
- OFDM 同步算法的描述 和源代码包括信道说明 和 各种参数的定义-OFDM synchronization algorithm descr iption and source code including the channel descr iption and definition of various parameters
costas
- 科斯塔斯载波同步的实现。采用了V_LOG代码编写~~~~ 可以直接编译使用-Costas carrier synchronization is achieved. Coding used V_LOG ~ ~ ~ ~ can direct the compiler to use
ofdmmatlabsimulation
- OFDM系统的完善性能仿真，包括同步、频偏、循环前缀等。-ofdm system simulation
PCM
- PCM采编器,帧长64字，字长为8位，地址分配如下： 帧同步码 0，1路 模拟通道 2-50路 数字通道 51-63路,串行输出数据，输出地址，模拟通道片选，数字通道片选-PCM editing device, frame length 64 characters, word length of 8-bit address as follows: frame synchronization yards 0,1 analog channels 2-50 channel digital channe
3
- 此程序为扩频程序，包括完整的通信编码，如信道估计，帧同步和载波同步等，，通过测试程序无误，欢迎下载-failed to translate
OFDM_ML_Sync_program
- OFDM系统ML同步算法仿真,可以直接跑.-ML synchronization algorithm for OFDM system simulation,can be directly run.
OFDM_sync
- ofdm基于循环前缀的同步算法，很实用，调试通过了的-ofdm synchronization algorithm based on cyclic prefix
bit_synchronize
- 位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog
mypll_qpsk
- MATALAB编写的QPSK用于载波同步的锁相环，其结构为平方环-MATALAB编写的QPSK的用于载波同步的锁相环，其结构为平方环
PLL
- 利用锁相环，比较好的实现了载波同步-PLL
timesyn
- 通信系统中的定时同步仿真，经过matlab调试和编译，可实现定时信息提取和误差估计检测-Timing synchronization in communication systems simulation, debug and compile through matlab, timing information can be extracted to achieve detection and error estimates! !