1.5-b/s Pipelined A/D behavior model 以及功能包,包括SNR INL DNL测试- 1.5-b/s Pipelined A/D behavior model Include SNR INL DNL test progrems

Simulation of direct digital synthesis sine wave in the MathCAD (10 bit ADC, 16-bit accumulator, 12-bit ROM, the clock frequency of 25MHz)