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leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
ddr
- 合众达DM6446试验箱学习实验源代码 ddr内存实验-the experimental source code DM6446 chamber ddr memory test
DDR_allegro
- 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
DDR_interface
- 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS
2812_mem
- dsp 2812 mem 测试程序 用于对ddr进行初始化实现内存读写，在ccs下开发-dsp 2812 mem test program is used to initialize achieve ddr memory, reading and writing, developed under the ccs
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
HY5DU121622CFP
- 64MB 512Mb, 16bit, DDR SDRAM MEMORY
DDR
- DDR内存条的设计资料，PC1600 and PC 21-DDR memory design data, PC1600 and PC 2100
DDR SDRAM Design Tutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
DDR_rev0.2
- DDR memory interface for PNX8935, PNX8932, PNX8335, PNX8332
Magnetic
- 磁珠专用于抑制信号线、电源线上的高频噪声和尖峰干扰，还具有吸收静电脉冲的能力。磁珠是用来吸收超高频信号，像一些RF电路，PLL，振荡电路，含超高频存储器电路（DDR SDRAM，RAMBUS等）都需要在电源输入部分加磁珠，而电感是一种蓄能元件，用在LC振荡电路，中低频的滤波电路等，其应用频率范围很少超过50MHZ。-Inhibition of signal lines dedicated to beads, the power line frequency noise and interfere
sdram_controller_latest.tar
- sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is me
memtest86-3.4
- 检测DDR错误的C语言程序Memtest3.4-C code detecting DDR memory errors,Memtest4.0
memtest86-3.5a
- 检测DDR内存错误的C语言程序Memtest3.5-C code detecting DDR memory errors,Memtest4.0
memtest86P-4.00
- 检测DDR内存错误的C语言程序Memtest4.0-C code detecting DDR memory errors,Memtest4.0
ug230.pdf
- The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific fe
dec6437_ddr_test
- 此例程是Seed dec6437评估版外部DDR存储器读写操作的示例程序，非常适合初学者入门DSP。-This routine is a sample program Seed dec6437 evaluation version of the External DDR memory read and write operations, ideal for the beginner to the DSP.
XAPP496---Memory
- 基于FPGA的内存设计资料，能给FPGA方便的使用DDR做很好的准备，很好的资源啊！-FPGA-based memory design information, ease of use give FPGA DDR do good preparation, good resource ah!
DDR设计系列
- 很好的PC内存条设计资料，如果你是内存设计的初学者，这里的资料很适合你，值得参考(Very good PC memory design information, if you are a beginner of memory design, the information here is very suitable for you, it is worth reference)