搜索资源列表
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
stopwatch.rar
- 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可,Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
vga_moving_pixel.rar
- 该项目在VGA显示器上显示一个移动的光点，并且光点的颜色还可以改变。使用VerilogHDL 语言编写，在Altera公司的QuartusII开发环境下验证通过。,The project in the VGA display to show a moving spot, and spot colors can be changed also. VerilogHDL language used in Altera' s development environment QuartusII ve
典型实例10.8 字符LCD接口的设计与实现
- 典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。,Typical examples of character LCD interface 10.8 The Des
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
VHDLprogram
- VHDL的程序包，包括LED控制，LCD控制、DAC0832接口电路、URAT、FSK\PSK\MASK调制、波形发生器等。适合工程参考-VHDL package, including the LED control, LCD control, DAC0832 Interface Circuit, URAT, FSK \ PSK \ MASK modulation, such as waveform generator. Reference for the project
ramvhdllib_06
- The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
vga_colors
- 该项目在VGA显示器上显示8色竖彩条。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on the monitor VGA color vertical color 8. VerilogHDL language used in Altera' s development environment QuartusII verification through.
vga_line
- 该项目在VGA显示器上显示一条从屏幕左上角开始，呈135度角的水平线。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on a VGA monitor from the top left corner of the screen to start, showing 135-degree angle of the horizon. VerilogHDL language used in Altera&
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
project
- 利用VHDL实现三个简单的程序：BCD加法器；ALU算术逻辑单元；简单密码锁设计，具有输入密码和数据比较两种功能，由M决定是写入还是开锁。而数据写入是采用列地址与输入数相结合的的方法，存入初始密码；开锁时，密码以输入，再输入的数据逐个与输入的一组数据比较，完全吻合则开锁。-The use of VHDL to accomplish three simple procedures: BCD adder ALU arithmetic logic unit simple lock design,
encoderdecoder
- this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year proj
VHDL
- 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
PS2andRS232
- 基于Verilog语言PS2接口和RS232接口的实现 有文档说明,工程实例.可用来学习Verilog语言.-Based on Verilog Language PS2 interface and RS232 interface implementation are documented, project examples. Can be used to learn the Verilog language.
project-1
- this a project design and its report of DESIGN AND IMPLEMENTATION OF LOGIC FUNCTIONS FOR DSP APPLICATIONS USING VHDL.
Project-Final-Requirements
- that a VHDL code with comparison between CLA and CRA adders modlism project
GPC-project
- 16 bit general purpose computer with VHDL code
calculator-project-VHDL-FPGA
- Calculator PROJECT FPGA ALTERA DE-2
DCD project
- vhdl code for 4 bit alu
aes-project-master
- aes project vhdl FPGA