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PhaseLockedLoop
- phase lock loop for coherent detection
gfuzzy
- 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
LMX2347
- VHDL code for LMX2347(Phase lock loop)
FAQLPC2xxxPLLFamilyPhaseLockLoop
- This application note describes the different blocks of the Phase Lock Loop in the LPC2000 family of Philips ARM7 Microprocessors.
synchronization
- 采用AFC技术来锁定频，采用Garden技术进行定时恢复，采用Costas环进行相位的锁定-Use technology to lock the frequency of AFC, using Garden timing recovery techniques using Costas loop for phase locking
pll_manual
- This book is document about "Phase lock loop"
LoopFilterMatrix
- phase lock loop pll toolbox tool
cppll
- Simulink analog phase lock loop
powerpll
- Simulink power phase lock loop
PLL_ars
- phase lock loop method
DPLL
- 模数转换的数字锁相环，代码中有详细的说明-digital phase lock loop
PLL
- Performance of Phase Lock Loop in fading channel
sim_PLL
- This shows how the phase lock loop can be designed and system parameter dendancy verified through simulation
PLL
- 在同步控制上，应用了“优先与抢占”的方式产生同步信号，纯硬件实现，简单可靠；使用了成熟的数字锁相环来跟踪同步信号。-A strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase-lock loop to track synchronization signal
3.2_SetPLL
- 流明ARM开发板设置PLL锁相环时钟示例程序，可以直接在IAR编译器上运行使用。-Lumens ARM development board PLL set phase lock loop clock example program, can direct IAR compilers run use.
ANOlog_TMS320F28335
- 本装置采用单相桥式DC-AC逆变电路结构，以TI公司的浮点数字信号控制器TMS320F28335 DSP为控制电路核心，采用规则采样法和DSP片内ePWM模块功能实现SPWM波。最大功率点跟踪（MPPT）采用了恒压跟踪法（CVT法）来实现，并用软件锁相环进行系统的同频、同相控制，控制灵活简单。采用DSP片内12位A/D对各模拟信号进行采集检测，简化了系统设计和成本。本装置具有良好的数字显示功能，采用CPLD自行设计驱动的4.3’’彩色液晶TFT LCD非常直观地完成了输出信号波形、频谱特性的在线
PLL
- The simulation file is the Phase lock loop with dq theory with unbalance input volatges
pll
- phase lock loop amjadmftah@hotmail.com
phase-lock-loop
- 编制Matlab仿真程 序。通过计算机仿真比较可以得出动态（捕获）性能，并画出改变某个参数条件下的响 应曲线，根据仿真结果更加直观、系统地分析环路的动态性能，为采样锁相环的研究和 工程设计提供参考。 -Through the computer simulation comparison can be obtained dynamic (capture) performance, and draw a change under a certain parameter condit