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秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可,Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
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ep2c5 实现 定时器
verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
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AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
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Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: a
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数字计时器的vhdl实现，quartus 和 modelsim 仿真-Digital timer vhdl achieve quartus and modelsim simulation
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