搜索资源列表
aes_encryption
- aes加密算法的VHDL代码实现，在FPGA芯片上调试过
aes加密算法实现，经过FPGA验证的
- aes加密算法实现，经过FPGA验证的！,aes encryption algorithm, after FPGA validation!
VHDL_AES_ZigBee
- 用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
FPGA
- 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code descr ipt
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
RIJNDAEL_DE_TOP
- AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
khalil2006_true_random_number_generator
- a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
aesencryption
- Aes encryption on Fpga
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
FPGA_128_AES_decryption
- 以FPGA具體實現的128-bit AES decryption，包括介紹文件以及源碼。-FPGA-based 128-bit AES decryption
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
aes_core.tar
- 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
aes-project-master
- aes project vhdl FPGA