搜索资源列表
-
0下载：
在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, th
-
-
0下载：
VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
-
-
0下载：
分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频,Divider vhdl descr iption of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
-
-
0下载：
This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
-
-
0下载：
Thia is VHDL code for clock divider
-
-
0下载：
a clock divider vhdl code
-
-
0下载：
vhdl的时钟信号分频 5分频电路代码 将任意频率5分频-vhdl clock signal frequency divider circuit 5 code any frequency band 5
-
-
0下载：
VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
-
-
0下载：
Package consists of two pdf files:
i)cdr project: theory and implementation of vhdl
ii)I2C bus controller: xilinx implementation of uC interface on CPLD
Package consists of 7 vhdl files:
string_detector: detects the continuous string of 11
-
-
0下载：
在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。
下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。
-In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the c
-
-
0下载：
VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。-VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.
-
-
0下载：
clock generator vhdl code
-
-
0下载：
该代码实现的是使用VHDL语言编程实现的FPGA上的时钟分频。通过修改代码中的参数改变FPGA的输出时钟频率。-The code implements the VHDL language programming on the FPGA clock divider. Changed by modifying the parameters in the code of the output clock frequency of the FPGA.
-
-
0下载：
很经典的时钟分频代码，直接拿来可以使用 使用VHDL语言编写！-Very classic clock divider code can be directly used to use using VHDL language!
-
-
0下载：
VHDL CODE FOR CLOCK DIVIDER
-
-
0下载：
VHDL代码实现分频器设计
分频器系统时钟20万分频
上升沿触发-VHDL code Divider Design
The system clock frequency divider 20 extremely
Rising edge triggered
-
-
0下载：
This the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit-This is the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit
-
-
0下载：
vhdl code which includes various codes of clock divider uart lcd etc
-
