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浮点加法器的VHDL算法设计 浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
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IEEE754 floating point adder
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一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
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32位浮点加法器。我第一次上载源码你就放过我吧，我就是想看一看加法器应该怎么做。-Floating point adder
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用c编写的用于测试浮点运算峰值的小程序。采用长度为N的浮点数组source[]自身相加N次的方法进行N*N次浮点加法运算来测试浮点加法峰值。-With c prepared for testing small peak floating-point operations procedures. Length of the floating-point numbers for the N group source [] the sum of N times its own methods of N
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利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
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基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
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本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
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该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
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Floating point adder
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it is verilog code for floating point adder
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浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
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floating point adder mul and sub in verilog code
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verilog implementation of the floating point adder
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一个浮点加法器，verilog描述，数据格式：高14位为尾数，低四位位指数（带符号数运算）-A floating point adder Verilog descr iption
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Implementation of 32-bits Floating Point Adder, based on IEEE 754 Standard
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floating point adder/subtractor in VHDL
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floating point adder
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Floating Point adder
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Fixed-Floating-Point-Adder-Multiplier with test bench
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