搜索资源列表
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3下载：
verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
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基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
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此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计
-The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code descr ipt
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高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
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高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
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一种基于FPGA的AES加解密算法设计与实现，对于对AES算法效率的研究有参考作用-FPGA-based AES encryption and decryption algorithm design and implementation of the AES algorithm for the efficiency of a reference
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论文介绍了AES算法在FPGA上的实现功能，对AES算法过程进行了优化。-This paper introduces the AES algorithm in FPGA implementation function of the AES algorithm to optimize the process.
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FPGA Implementation of AES Encryption and Decryption
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Pipelined Implementation of AES Encryption Based on FPGA
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基于ＦＰＧＡ的ＡＥＳ加密算法的实现 由于其较高的保密级别，AES算法被用来替代DES和3一DES，以适应更为严苛的数据加密需要。-FPGA Implementation of Real-Time Adaptive Image Thresholding
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基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.
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Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be
implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design
time while FPGA based implementation
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AES GCM 算法介绍，对AES算法实现有一定帮助。-This document aims to explore hardware implementation of GCM-AES mode of operation specifically targeting FPGA [1] (Field Programmable Gate Arrays). The aim of such an implementation is to benchmark GCM-AES on FPGA in term
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This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware
implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications,
since it is tuned to specific FPGA logi
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The AES-128 implementation as depicted in Figure 3 has
been implemented on the FPGA. This required an initial
round key addition followed by ten rounds of S-Box.
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We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
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各种密码算法的FPGA实现情况
1.AES算法FPGA实现分析
2.DES加密算法的高速FPGA实现
3.RSA加解密运算的FPGA硬件实现研究(FPGA implementation of various cryptographic algorithms)
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