搜索资源列表
rs-codec-8-16
- 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
16-bit数的偶数奇偶校验
- 16-bit数的偶数奇偶校验及阶乘运算，用verilog写-16-bit number of even parity and factorial computation, written using Verilog
9.16 fifoasi
- 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
mutl16 实现16位移位乘法和除法
- 实现16位移位，可以实现乘法和除法。满足设计要求，实现代码简短，用verilog完成方便，容易操作。-Achieve 16-bit shift, multiplication and division can be achieved. Meet the design requirements to achieve a short code, complete with verilog convenient, easy to operate.
用EPM1270实现的1602液晶驱动Verilog
- 用EPM1270实现的1602液晶驱动Verilog,EPM1270 achieved by 1602 LCD driver Verilog
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
16QAM
- 16QAM调制与解调的Verilog语言的功能实现-the realization of 16QAM modulation and demodulation on Verilog language
IIR_Filter_8
- verilog实现8阶的iir滤波器。对于刚学习verilog的朋友来说是一个易懂的学习资料。-verilog order to achieve the iir filter 8. For just learning verilog friend is a easy to understand learning materials.
1602
- verilog HDL语言编写的完整工程，功能是点亮1602lcd，在lcd上显示英文和数字-verilog HDL languages complete works, the functions of light 1602lcd, in the lcd display in English and the number of
lcd
- 基于fpga的tft液晶驱动，控制器是ILI9325，是verilog写的，16位并口模式，我上网上搜索了很久都没找到的，-Fpga based on the tft LCD driver, controller ILI9325, is written in verilog, 16-bit parallel mode, on-line search for a long time I did not find,
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
verilog.DA.FIR..
- 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
fir
- 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
cpu_16bit
- design cpu 16 bits by verilog HDL.
16_bits_CPU_verilog_code
- 利用Verilog设计的16位CPU的设计案例-the example of 16 bits CPU using verilog
16QAM
- This Verilog HDL file for 16 QAM mapper-This is Verilog HDL file for 16 QAM mapper
BCH[31-16]-with-BPSK-MFSK
- comperation of performance of BCH [31 16] code with BPSK and MFSK
16 bit signed number multiplier
- 16位有符号数乘法器，使用Booth编码和华莱士树，提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)
Verilog的135个经典设计实例
- Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例
现有16位寄存器。初始值为0
- 现有16位寄存器。初始值为0。每个时钟周期寄存器的值会左移1位，并且将输入的数据data_in作为寄存器的最低位，寄存器原来的最高位将被丢弃。要求每个周期实时输出该16位寄存器对7求余的余数data_out[20]。(Existing 16 bit register. The initial value is 0. The value of each clock cycle register will shift 1 bit to the left, and the input data wil