搜索资源列表
cntl_ddr3(xilinx)
- xilinx ddr3最新VHDL代码,通过调试
DDR3_user_design
- 在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制-On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control
ml605_MIG_rdf0011_13.4_c
- 该参考程序是基于xilinx ml605开发板的一个DDR3参考设计，源文件包含相应的管脚约束文件。-The reference procedure is based on xilinx ml605 development board a DDR3 reference design source file contains the corresponding pin constraint file.
PCIE_DMA_DDR3_verilog_design
- 基于xilinx fpga的pci-e到dma再到ddr3的数据传输完整设计-PCIE_DMA_DDR3 verilog reference design
DDR3design-on-xilinx
- 在xilinx平台上实现的ddr3的设计，verilog-ddr3,design on xilinx,verilog
ug586_7Series_MIS-xi
- 有关于xilinx平台DDR3 ip core介绍-xilinx ip core
xilinx_DDR3-ctl_code
- VHDL语言，xilinx,ddr3 控制代码，已实现-VHDL xilinx DDR3ctl code
lib_dmarc_1d_v1
- xilinx DDR3控制器读数据控制,对读控制器进行了很好的读写封装，可以支持连续和非连续读写。-xilinx DDR3 controller reads the data controller, the read controller package to read and write well, you can support continuous and sequential read and write.
xilinx_ddr3
- xilinx ddr3 开发， 实测好用-xilinx ddr3 development, found handy
DDR3_128M16bit_2Port64bit
- Xilinx spartan6 DDR3驱动，编程语言Verilog，基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
axi_master
- DDR3 控制器，axi4_full 模式， burst长度为16，应用于xilinx平台。-DDR3 interface controller， axi4_full working mode with burst length 16, can operate on the xilinx platform.
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
11_ddr3_test
- Xilinx Spartan-6 DDR3 test code
35_OV7725_VGA_DDR3_LX16_joint
- 多目摄像头同屏显示，实现图像分割，xilinx公司芯片，ISE平台开发(Multi camera on the same screen display, image segmentation, Xilinx company chip, ISE platform development)
11_ddr3_test
- spartan6 ddr3 test with FPGA communicate
DDR3_A4
- xilinx FPGA A7 驱动DDR3的DEMO例程(DEMO routines driven by Xilinx FPGA A7 for DDR3)
XILINX平台DDR3设计教程
- 从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)
spartan6 ddr3 controler
- xilinx spartan6 ddr3 test demo
test_ddr3
- 基于XILINX K7系列FPGA实现5120*5120分辨率20帧的DDR3读写，发送到海思3559,HDMI显示。(Based on Xilinx K7 series FPGA to achieve 5120*5120 resolution of 20 frames of DDR3 read and write, sent to the Hays 3559,HDMI display.)