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adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
add32
- 一个32位超前进位加法器 不一样的算法 简单实用-An 32-bit look-ahead adder not the same as the algorithm
adder32_carry_select
- 用Hspice编写的32位超前进位加进位选择快速加法器，经验证速度达0.6ns-An adder32_carry_select nse Hspice.
adder
- 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
4-ahead_Adder
- 用Verilog HDL语言实现超前进位加法器的逻辑功能,通过ModelSim软件对4位超前进位加法器设计的仿真.-With the Verilog HDL language-ahead adder logic functions, by ModelSim software 4-ahead adder design simulation.
add16_32
- 十六位加法器，超前进位加法器，总共三十二位。 -Sixteen adder, look-ahead adder, a total of Thirty.
Verilog_32bit_Adder
- 32位加法器，使用超前进位的方法，在速度和能耗上做了较好的折中-32bit adder
four-lookahead-adder
- verilog_HDL-四位超前进位加法器,学习资料，可以方便的用-verilog_HDL-four lookahead adder, learning materials, you can easily use
4weichaoqianjinweiqi_verilog
- 四位超前进位加法器的verilog实现。用VHDL语言，附加检验tb.v-Four lookahead adder verilog implementation. VHDL language, additional testing tb.v
pre_counter
- 超前进位加法器，硬件实现，FPGA,verilog-Carry lookahead adder, hardware implementation, FPGA