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stopwatch
- VHDL秒表设计，硬件环境为NEXYS4开发板，有暂停功能，7段数码管显示。-VHDL stopwatch design, the hardware environment for the NEXYS4 development board, a pause function, 7 digital tube display.
CompuertAnd.tar
- And gate in Verilog for Nexys4
NEXYS4.UCF
- constraint for nexys4
38DEC
- 基于Nexys4开发板的3-8译码器的实现(Implementation of 3-8 decoder based on Nexys4 development board)