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Tdiaantikonggh
- 本设计是本人的课程设计,一种基于VHDL的电梯控制器的设计,能够实现12层电电梯控制,上下开关,关门延时,提前关门,状态显示出来,通过波形仿真进行观看结果 -The design is my curriculum design, based on VHDL design of the elevator controller to achieve the 12-layer electric elevator control, and switch up and down, closing de
SDF-DIF-FFT-pipelined
- vhdl code for pipelined single delay feedback radix 2 square FFT
cntr_4bit
- This the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit-This is the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit
xgq_not
- 相关器的相关VHDL语言。其中加上延迟,20ns 软硬件仿真均实现-Related VHDL language correlator. Which coupled with the delay, 20ns simulation software and hardware have achieved