搜索资源列表
jtag_verilog
- verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
EHERNETIPcore
- 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码
在ISE下调用计数器IP核
- 非常简单的计数器，在ISE下调用计数器IP核，使用verilog开发得到的。-Very simple counter, under the invocation counter in the ISE IP cores, development has been the use verilog.
EEthhernet_vet
- Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核，对学习verilog语言与以太网有非常大帮助。 -Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet.
vFFT_veriloge
- verilog实现的FFT变换，经硬件测试其功能与AAltera的FFT IP核相近， -verilog realization of the FFT algorithm, its function is similar to the FFT IP AAltera the nuclear test by the hardware,
i2c_master
- I2C master模式的IP core（verilog）-I2C master mode IP core (verilog)
IPCores_iic_8051
- I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
cordic
- Altera 的CORDIC IP核，Verilog HDL-Altera CORDIC IP core, Verilog HDL
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code
IPcore
- verilog IP核调用子程序，源码-Verilog IP core call subroutine, the source code
UDP
- 用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用-Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role
rtl_1795
- Developper:mathswork Arm IP Core Verilog This IP core is an ARM clone. It has the same architecture of ARM v4. Its main feature lists: Not support coprocessor instructions Not support THUMB instruction set All interrupts
LED
- FPGA中实现led流水灯,通过Verilog语言编程，程序中调用了xilinx公司提供的时钟分频IP CORE-This file is to achiece led like water
5_bluetooth_uart
- 基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。封装自己的蓝牙串口IP。蓝牙串口数据传输需要三个模块，分别是波特率生成模块，接收模块和发送模块。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. Package your own Bluetooth serial port IP. Bluetooth serial da
lvds
- XILINX 官方的LVDS IP核，亲测可用。。。。。(XILINX official LVDS IP kernel, pro test available.....)
fft512
- 基于verilog IP核的FFT工程，512位FFT运算，(FFT engineering based on Verilog IP kernel and 512 bit FFT operation,)
基于FPGA和IP核的FIR低通滤波器
- 用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
FFT v1
- IP core fft verilog code example
高大上欧美风商务PPT模板
- JPEG_d IP Core Verilog crypted source