Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II

用于制作ALTERA FPGA的下载线（USB_BLASTER）的CPLD逻辑代码（VHDL代码）。-USB BLASTER CODE DDFP SDFA SDE DSF DOD DOE DOE DOIII DEG SDAF, FSGR SE.

这是altera CPLD\FPGA USB blaster的驱动，完全可用。-This is altera CPLD/FPGA USB blaster driver, completely available.