基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.

This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logi

The AES-128 implementation as depicted in Figure 3 has been implemented on the FPGA. This required an initial round key addition followed by ten rounds of S-Box.