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mips_project
- 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
mipsdesign
- mips核代码，Verilog写的，希望对大家有用-mips core code, Verilog written
ask10
- This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can
singlecycle_mips
- single cycle mips design by verilog.
mips789.tar
- 一个功能很完善，很强大的mips处理器，verilog编写的-A feature is perfect, very strong mips processor, verilog prepared
code
- 是用verilog写的带uart的简单controller，使用的是mips指令，用modelsim仿真，波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
cache
- 基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
ALU
- MIPS ALU written using Verilog HDL. Computer structure project
pipeline_mipscpu
- 运用Verilog语言实现MIPS五级CPU的功能，能下载实现-5-level MIPS CPU based on Verilog
multi_cpu
- 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
MIPS
- MIPs Processor in Verilog
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
openmips
- 一个开源mips处理器verilog 源码-wishbone interface wishbone interface
sc_computer_2
- Verilog单周期CPU实现,可以实现简单的mips指令，附Verilog源码-Verilog achieve single-cycle CPU
MIPS-Verilog-master
- MIPS R3000 microprocessor core
wuhao
- C语言编程以及MIPS汇编语言还有logisim的简单实现，算法(C language programming and MIPS assembly language, as well as a simple implementation of logisim, algorithm)