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usb1.1
- USB 1.1的verilog代码，已通过fpga验证
基于USB-ATA接口的海量存储器的设计与实现
- 介绍了一种基于通用可编程接口的通用串行总线-高级技术配件解决方案，将普通硬盘转化为Usb Mass Storage.-introduces a general programmable interface based on the Universal Serial Bus-senior technical accessories solution that will drive into ordinary Usb Mass Storage.
verilog
- source code for USB 2.0 fonction core in verilog
usb_ctl
- CH372 USB芯片 采用Verilog语言，实现FPGA与上位机通信，按键触发FPGA向上位机传数，USB测试软件向FPGA传数-CH372 USB chip using Verilog language, to achieve FPGA and PC communications, key trigger FPGA pass up crew numbers, USB test software to pass several FPGA
usb
- USB slave: It is contain a USB slave design written in verilog language. It is a interface between USB host and Functions such as memory, Keyboard, mouse and so on.-SB slave: It is contain a USB slave design written in verilog language. It is a inter
verilog
- 关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。-About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.
vSPI-master
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter