搜索资源列表
Altera_uart_Verilog
- FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source
BCH（15,7,2)
- bch（15,7,2）decode and encode in verilog hdl N=15，K=7，T=2时的BCH码编码：
Verilog_Hdl48FIR
- verilog hdl fir 48阶-verilog hdl fir
verilog_scramble.v.tar
- 扰码程序，利用Verilog语言实现，适合各种通信系统的扰码。-scramble code,verilog hdl,adapt to many communication systems
C6474L_EVM_RTL
- TI C6474评估板的fpga源代码，初始化板子必备代码，Verilog HDL硬件语言编写。-TI C6474 evaluation board fpga source code, the code necessary to initialize the board, Verilog HDL hardware language.
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code