搜索资源列表
SynplifyPro_QuartusII_Ver5_v4_1
- synplify 与quartus 进行FPGA综合设计文档-Synplify and Quartus FPGA integrated design documents for
EP1C3_12_10_PHAS
- 基于FPGA的移相式DDS正弦信号发生器的VHDL源代码，压缩包里是在Quartus里做的工程，FPGA用的是Cyclone1C3系列-FPGA-based phase-shifting of the DDS signal generator sine VHDL source code, compressed in the bag is done in Quartus Engineering, FPGA is used Cyclone1C3 Series
EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
dds_v3_test3
- DDS控制器在FPGA上的实现，使用Quartus II8.1开发环境，使用Altera 原理图设计方法，10位宽度，配合dac9-DDS controller in the FPGA on the realization of Quartus II8.1 use development environment, the use of Altera schematic design, 10-bit width, with dac900
ChangePinFormat
- Protel画FPGA原理图时导出的引脚文件，不能直接用于Quartus的的引脚绑定。该程序可以将其格式转换为Quartus认可的文件。大家也可根据自己情况修改。-Protel schematic drawing FPGA pin when the exported file can not be directly used in the Quartus pin bindings. The program can be converted to the format approved Quart
FPGAclock
- 关于基于Quartus ii的FPGA系统时钟详细的讲解-the clock in FPGA design
signaltap
- FPGA基于alter quartus ii的signaltap使用指南-FPGA-based alter quartus ii signaltap user guide
weitongbu
- 基于fpga的位同步信号提取仿真 使用vhdl语言 quartus-To use vhdl language quartus fpga bit synchronization signal extraction-based simulation
abc
- 在Quartus II 9.1下开发FPGA/CPLD程序的使用教程操作笔记-Quartus II 9.1 developed under the operation of the FPGA/CPLD program using the tutorial notes
quartus
- 用于脉搏检测的FPGA代码,内含计数器，译码器-for FPGA
verilogSerialcommunication
- FPGA实现RS-232串口收发的仿真过程（Quartus+Synplify+ModelSim）-On the RS-232 online asynchronous transceiver introduced a lot, recently there groping to do with the ModelSim timing simulation, combined with the online reference and their own thinking, do this thin
VHDLqiangdaqi
- 基于Quartus的抢答器的设计，用VHDL硬件电路设计实现的模拟电路，用FPGA开发板可看到效果，一共八个按钮，有复位键-Quartus Responder based design using VHDL hardware circuit design and implementation of analog circuits, FPGA development board can see the results, a total of eight buttons, with reset bu
11223
- 通过使用EDA工具，设计实现简易音乐播放器。在结合各个数字功能模块并利用FPGA系统本身丰富的物理资源的同时，将音乐的乐谱设计在FPGA内部，在Quartus II环境下，采用Verilog HDL 语言实现音乐合成器和播放系统。-By using EDA tools, design and implementation simple music player. The integration of the various functional modules and the use of F
wave
- Quartus 个工程文件源代码，功能产生方波，板子是FPGA-Quartus a project file source code, function generates a square wave, the board is FPGA
fpga-radio
- FPGA radio using Quartus or MAtlab
Desktop
- 可以用于直接生成FPGA quartus等项目需要的dat文件(Can be used to directly generate FPGA, quartus and other projects required by the dat file)
Verilog_Beep
- 用Verilog语言，quartus软件，实现fpga开发板上按dou lai mi fa等7个音实现按键弹钢琴(Verilog language, quartus software, to achieve fpga development board by dou lai mi fa 7 sound to achieve the key to play the piano)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
crc_write
- 基于quartus II的CRC16校验代码，并实现了Modlsim实现了仿真验证(The CRC16 check code based on Quartus II and the realization of the simulation verification by Modlsim)
071162程序
- 设计一个用于篮球比赛的定时器。要求： （1）定时时间为24秒，按递减方式计时，每隔1秒，定时器减1； （2）定时器的时间用两位数码管显示； （3）设置两个外部控制开关，开关K1控制定时器的直接复位/启动计时，开关K2控制定时器的暂停/连续计时；当定时器递减计时到零（即定时时间到）时，定时器保持零不变，同时发出报警信号，报警信号用一个发光二极管指示。 （4）输入时钟脉冲的频率为50MHz。 （5）用Verilog HDL语言设计，用Modelsim软件做功能仿真，用Quartus II综