verilog编写，含三路正弦信号发生器，三路数据乒乓缓存模块。乒乓缓存读写控制采用三段式状态机实现。-The project contains a 3-channel sine generator and a 3-channel ping-pong buffer which is written in verilog. The write and read control of buffer is implemented in 3-segment FSM.

同步先见先出缓冲器。用一个时钟。用Verilog HDL实验的。-Synchronization seer, first-out buffer. With a clock. Experiment with Verilog HDL.