搜索资源列表
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
shizhong
- 用vhdl语言描述时钟的功能，并通过七段译码显示输出。-VHDL language used to describe the function of the clock and through the Seven-Segment display decoder output.
led778
- 用vhdl语言控制七段显示管和八个LED灯的程序，并通过下载验证。-VHDL language used to control Seven-Segment display tube and eight LED lights procedures and verification by downloading.
351_3
- 7 segment display for spartan3 vhdl code
led
- 七段LED数码显示器是数字系统中常用的数码显示元件，二进制数不能直接在LED数码管上显示，需要用一个BCD七段译码器进行译码。下图给出了一个七段显示译码器的框图及相应的七段LED数码管的示意图。-Seven-segment LED digital display is commonly used in digital systems digital display devices, a binary number can not be directly displayed on the LED
LED
- 该程序用VHDL语言实现了LED七段显示的功能-The program implemented using VHDL language features LED seven-segment display
gate_led
- 点亮LED7段数码管，使其可以显示从9到0这10个数字，编写语言为VHDL-Light LED7 segment digital tube, so that it can display from 9-0 of these 10 figures, prepared for the VHDL language
Seven-Segment-LED-Decoder
- 简单的七段数码管译码器vhdl程序,比较基础,适合初学者练习使用-Simple seven-segment decoder vhdl program basis for comparison, for beginners to use.
seven_segdisp
- 基于vhdl的7段码显示内核程序，用nios 2编写，有助于nios的学习-Based vhdl 7 segment display kernel program nios 2 preparation help nios learning
Timer
- Nexys 3 seven segment display module written in VHDL
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
EjemploDisplay
- VHDL code for a 7-Segment display.
3-example_dt_2
- Vhdl编写的数码管驱动，动态7段码，FPGA实验板，Xilinx ISE实验环境-Vhdl write digital tube drive, dynamic 7-segment code, FPGA experimental board, Xilinx ISE experimental environment
vhdl---calculator
- 基于vhdl语言编写的简易计算器程序，其中主要功能有加减乘和清除，确定等，可实习现连续运算。输出使用七段数码管输出，输入采用拨码开关的方式输入。若计算结果超过99999，蜂鸣器自动报警。-Vhdl language based on simple calculator program, where the main function, subtraction, multiplication and clear, determined, can now practice continuous op
shiyan1
- 7段数码管显示译码和扫描电路的设计的VHDL语言，可以直接使用 -7-segment LED display decoding and scanning circuit VHDL language design, can be used directly
Seven_segment_display
- SEVEN SEGMENT DISPLAY, ON VHDL, ISE DESIGN SUITE 14.7, XILINX
八位数码管的动态显示VHDL程序
- 7段数码管动态显示程序，高频动态显示多位数(7 segment digital tube dynamic display program)
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
plj
- 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6