搜索资源列表
LCD.基于FPGA的LCD1602驱动
- 基于FPGA的LCD1602驱动，verilog代码，已经调试成功,LCD1602-driven FPGA-based, verilog code debugging has been successful
CAcode
- CA码的FPGA实现，verilog编写-CA Code of FPGA implementation, verilog preparation
lcd1602-verilog
- 基于QuartusII的LCD1602-Verilog 源代码，可以直接应用于FPGA开发板。-QuartusII based on the LCD1602-Verilog source code, can be directly applied to FPGA development board.
63535309sram
- verilog编写的读写SRAM的源码，包括sram的读写控制-SRAM read and write verilog source code written in, including the sram to read and write control
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
Verilog
- 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use
lcd
- 基于fpga的lcd1602的verilog程序代码，可实现移动显示数字和英文字母-Verilog fpga lcd1602 the program code, mobile numbers and letters
motor_basic
- 基于FPGA的直流电机闭环控制，Verilog HDL编写的源代码-DC motor closed-loop control based on FPGA, Verilog source code written in HDL DC motor closed-loop control based on FPGA, the Verilog HDL source code
CF-verilog
- CF卡的经典整套资料，有芯片手册、接口说明、verilog源码、参考电路，很适合FPGA开发者研究CF卡-Classic set of data on the CF card with a chip manuals, interface descr iption, verilog source code, reference circuit, it is suitable for FPGA developers to study the CF card
nor_flash_verilog
- fpga verilog实现 S29GL256S 系列 并行 nor flash 的读写擦除操作功能。 verilog源代码。-Verilog S29GL256S to achieve FPGA series parallel flash nor read and write erase operation function. Verilog source code
chengfaqi
- 经过改良的乘法器，硬件实现，FPGA，verilog源码-Improved multiplier, hardware implementation, FPGA, Verilog source code
myCpu2
- CPU硬件实现，能运行基本程序，FPGA，verilog源码-CPU hardware implementation, can run the basic procedures, FPGA, Verilog source code
至简设计法--VGA_显示动画
- 至简设计法--VGA显示动画 工程说明 本工程VGA显示要求：复位后，屏幕中央显示直径为10的蓝色圆点；按下按键0，圆点图像逐渐变大，直至直径变为400；再按一下按键0，圆点逐渐变小，直到直径为10。此过程要有明显的动画效果。 案例补充说明 本设计的VGA图像动态显示是基于FPGA实现的，采用了Verilog HDL语言编写，再加上有明德扬的至简设计法作为技术支撑，可使程序代码简洁且执行效率高。(Engineering descr iption The engineering requirem
SPI协议的Verilog_实现
- spi串口原理介绍，并附有verilog编程代码，有助于在FPGA上实现。(The principle of SPI serial, and with a Verilog programming code, contribute to the implementation on FPGA.)
cam2hdmi_top
- camera to hdmi verilog code for xilinx fpga
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
crc_write
- 基于quartus II的CRC16校验代码，并实现了Modlsim实现了仿真验证(The CRC16 check code based on Quartus II and the realization of the simulation verification by Modlsim)
key_filter
- 采用Verilog语言的编写按键防抖代码，并通过modlesim进行验证(Using the Verilog language to write key anti - chattering code and verify it by modlesim)
CY7C68013 Verilog test
- CY7C68013固件程序以及 FPGA测试Verilog程序，源代码(CY7C68013 firmware program FPGA test Verilog program, source code)