搜索资源列表
iicreciver
- iic slave verilog hdl code
smi_rw
- 基于IEEE802.3标准的SMII网络通信的VERILOG实现
Verilog
- Verilog实现的以太网接口源程序代码
led
- fpga led verilog language code
viterbi.v
- viterbi的verilog文件，很实用的。
TCPIP
- 用C实现的完整TCP/IP协议源代码,私家珍藏的宝贝-the code of TCP/IP protocol realized by C. It s very valuable.
htmldlg_demo
- 在对话框内显示html的程序- Demonstrates html in the dialog box the procedure
IEEE_standard_Verilog_HDL1364_2001
- IEEE standard Verilog HDL1364-2001.pdf Verilog 学习必备资料-IEEE standard Verilog HDL1364-2001.pdfVerilog learning essential information
Verilog_NBA
- Verilog非阻塞赋值的仿真/综合问题-Non-blocking assignment Verilog simulation/synthesis
v2html
- Verilog 2 Html Perl Source Code
mac_controller
- 用verilog编写实现的以太网控制器（MAC）源码，解压后用ISE打开工程即可。-Prepared using verilog implementation Ethernet Controller (MAC) source code, open the project after decompression can be used ISE.
tongxinyuanli
- 数字通信原理 曹志刚版的SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用--Digital Communication Principles of CAO Zhi-gang version of the SPI bus, under the Verilog hardware descr iption language implementation, including Master mode and slave mode of impl
Provided_block_SWLAN
- simplified wlan with verilog in project
slave-ram-verilog
- ram代码 用verilog写的，有文字说明-verilog code of ram
MAC_verilog
- 以太网MAC网卡的Verilog源代码，可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time.
PTP1588
- 此设计主要是应用于对时，符合PTP1588通信协议，verilog描述-This design is mainly used in pairs, in line with PTP1588 communication protocols, verilog descr iption
Examples-for-Self-Study_book
- more than 25 examples to learn Verilog and VHDL with model simulation results
wtut_ver
- Verilog语言开发环境ISE例程，适合于初学者ISE Verilog language development environment routines, suitable for beginners-For the Verilog language development environment ISE routine suitable for beginners ISE Verilog language development environment routines, suitable
digital_watch_lcd_core
- a verilog code for digital clock
i2c-verilog-vhdl
- I2C总线VHDL/Verilog HDL源码 通过仿真验证正确，希望对大家有用-I2C bus VHDL/Verilog HDL source code is verified by simulation is correct, we hope to useful