搜索资源列表
rom_des
- DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
md5_latest[1][1].tar
- MD5算法verilog代码，很不错的，可以互相交流学习-MD5 algorithm verilog code, and a very good
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
sha1_verilog
- 安全散列算法的另一种verilog实现，对面积的要求更小，但损失了速度，但在一般系统中，完全可以满足大部分需要了-Secure Hash Algorithm another Verilog realization of the demands of a smaller area, but a loss of speed, but in the general system, fully satisfy the needs of the most
8086IP
- 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
GF_MUL
- Galois域乘法器的Verilog源码 广泛用于信道编码、计算机代数及椭圆曲线加密等-Galois field multipliers are widely used in the Verilog source channel coding, computer algebra and elliptic curve encryption
Linux_bc
- 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xili
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
rsa
- 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
dsp_radar
- radar detecttion in verilog
use_3_shoft
- SHA-1的verilog程序，经过优化的了，希望可以对大家有帮助-SHA-1 of the verilog program, optimized, and hope that we can help you
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
aes_crypto_core_latest.tar
- verilog code for aes
aes_thesis_v1.0
- AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
rtl
- 基于脉动结构的有限域乘法器，verilog代码-Based on the pulse of the structure of finite field multipliers, verilog code
AES_verilog
- AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
DES_Encrypt_Decrypt_Verilog
- DES加密算法的Verilog HDL实现，带模式选择端口，可以实现加密和解密，已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
topic
- DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.