安全散列函数的VERILOG实现，通过了fpga验证，在系统正可以直接当IP盒应用-Secure Hash Function VERILOG achieve, through the FPGA verification, the system is can be directly applied when the IP box

哈希函数加密算法的高速实现,结合"循环打开"和"路径优先"两大技术,提出基于FPGA的SHA加密算法高速实现.-High-speed implementation of the hash function encryption algorithm, combining the two technologies " loop open" and " Path First proposed to achieve high-speed FPGA-based SHA encry

hash加速器的verilog实现，也用于fpga或asic-hash verilog rtl