搜索资源列表
rtl
- 基于脉动结构的有限域乘法器，verilog代码-Based on the pulse of the structure of finite field multipliers, verilog code
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
rtl_wangjiangxing
- ecc椭圆算法RTL,verilog经过验证-ecc verilog
HASH
- hash加速器的verilog实现，也用于fpga或asic-hash verilog rtl
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl