搜索资源列表
RS_Verilog
- RS码的FPGA实现,verilog语言形式,好参考资料-FPGA realization of RS code, verilog language form, a good reference
verilogHDL
- RS(31,15)译码关键步骤的veilog HDL算法实现,包括关键方程求解,错误位置估计,错误值计算等-RS (31,15) decoding a key step in the algorithm veilog HDL, including key equations, position estimation error, error value, such as
rs-code
- VHDL Code for D-Flip Flop & Matching Unit