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fir
- 基于FPGA 的dsp模块下建立的语音压缩中的混合滤波器组-FPGA-based dsp established under the voice compression modules in the hybrid filter banks
DDFS_verilog
- 直接数字频率综合器,采用ROM压缩法,经过FPGA验证和AISC实现-Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation