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USBipcore
- usb1.1 ip核,使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
usb11_phy_translation_latest.tar
- USB1.1 物理层实现 VHDL,opencore上也是可以下载的,是1.1的版本,比较简单,但是很实用,对于入门usb还是有帮助的-usb11_phy_translation_latest version
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code