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CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera fpga CPLD design (Basics) CD-ROM1
key_filter
- 用于fpga的按键消抖的verilog文件，经过modelsim仿真和下板验证。-verilog file for fpga key debounce, after modelsim simulation and verification under the plate.