基于vhdl硬件描述语言的8位加法器的设计-Based on the design of the 8-bit adder VHDL hardware descr iption language

VHDL code of full adder

The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl-The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl