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freerisc8_11.zip
- 8位RISC cpu的verilog编程 SOURCECODE,8 RISC cpu verilog programs SOURCECODE
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC cpu 内核源码（verilog 版）-verilogRISC8 cpu CORE8-bit RISC cpu core source (verilog version)
cpu
- verilog编写cpu： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like cpu using verilog
cpu
- 一个多周期cpu的完整设计，quartus平台，verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle cpu design, quartus platform, verilog implementation, includes lab reports, and a detailed menu of each module
cpu
- verilog编写的简单的cpu，用于参考，已经过仿真-verilog prepared by a simple cpu, for reference, has been simulation
cpu
- 5 stage pipeline cpu, verilog HDL code-5 stage pipeline cpu
cpu
- 32位5级流水线cpu设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline cpu
RISC
- hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the verilog ah
riscpu
- 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
1-in_clk
- verilog HDL编写的4条指令cpu-verilog HDL prepared four instructions cpu
TINY3
- verilog 编写的tiny cpu 代码，可实现简单的指令和计算-verilog prepared tiny cpu code, can be simple instructions and the calculation
mipscpu
- MIPS cpu tested in Icarus verilog
cpu(FinalWithYS)
- verilog实现的八位cpu，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight cpu, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
cpu
- verilog实现的一个简单的cpu，大家可下载去瞅瞅啊-verilog to achieve a simple cpu, you can download to Chou Chou ah
cpu
- cpu with 8 bits in VHDL verilog Code
cpu
- 一个完整的流水cpu设计，quartus平台，verilog实现-cpu design a complete water, quartus platform, verilog realization
32bitcpu
- 用verilog写的32位cpu源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit cpu verilog source code, assembly language can be achieved through the addition, subtraction and other operations righ
cpu-master
- 单周期cpu的verilog源码实现，基于Vivado(Single cycle cpu verilog source code implementation, based on Vivado)