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用verilog写的对ad0809的控制
- 用verilog写的对ad0809的控制，完整工程，希望对大家能有帮助,Written using verilog for ad0809 control, complete works, in the hope that we can help
fifo-verilog
- 自己设计的一种fifo寄存器，用verilog 编写，QUARTUS II下验证-Own design of a fifo register, with verilog preparation, QUARTUS II certification under
FPGA_fifo
- 使用verilog编写的同步fifo，可通过设置程序中的DEPTH设置fifo的深度，fifo_WRITE_CLOCK上升沿向fifo中写入数据， fifo_READ_CLOCK上升沿读取数据。本程序对fifo上层操作简单实用。-Prepared by the use of verilog synchronous fifo, through the setup program in the fifo depth DEPTH settings, fifo_WRITE_CLOCK rising
fifo
- 用verilOG写的fifo程序，可以直接引用经本人测试-verilOG written using fifo procedures, can be directly invoked by the I test
use_SRAM_design_fifo.pdf
- 利用sram技术设计的一个fifo-failed to translate
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for