搜索资源列表
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两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
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基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
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用verilog实现异步FIFO，代码中有两个模块，使用时注意顶层模块和底层模块，用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
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verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
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verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
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这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
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基于FPGA的软FIFO代码实现，双时钟，异步。VERILOG-FPGA-based soft FIFO code, two clocks, asynchronous. VERILOG
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Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
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异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
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fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
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verilog code for gray counter,synchronous and asynchronous fifo
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同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
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asynchronous fifo with pulse input
write by verilog code
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异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
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verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
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Verilog语言写的异步fifo，包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code
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异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
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自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
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