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CyclonePLL
- Cyclone™ FPGA具有锁相环(PLL)和全局时钟网络,提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出,进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件,就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟,使内部工作的时钟频率比外部时钟更高,时钟延迟和时钟偏移最小,减小或调整时钟
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- FPGA设计中几个基本问题的分析及解决 多时钟系统,时钟设计,时钟歪斜,门控时钟,毛刺信号及其消除,FPGA中的延时设计,FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the d
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
gateclockexcursionanalysis
- 门控时钟与时钟偏移分析,详解门控时钟偏移的产生和解决办法。-Gated clock and clock skew analysis Xiangjie gated clock skew of the generation and solution.
16X16dianzhenxiegunshiyan
- 16X16点阵斜移滚动显示实验,及其源代码-16X16 dot matrix skew scroll through the experiment, and its source code
del_skew
- 按键消抖的verilog代码,在fpga开发板上可用,有按键功能的设计如果不消除抖动,可能会造成误触发-a cut key skew verilog code ,it can work on fpga card,key cut skew is very importent,the design may have error without the code.