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移动8位乘法器
- vhdl 乘法器
Multiplier.rar
- 乘法器 所占资源很少 很好的一个乘法器 史书上的一个例子 说得很好啊,Multiplier good share of scarce resources in the history books on a multiplier an example of very good
mux4
- 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
61EDA_D721
- 8*8乘法器设计，和大家共享，互相学习，共同进步-8* 8 multiplier design, and for all to share and learn from each other and progress together
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
Pentium
- 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
chengfaqi4
- 用VHDL实现四位乘法器，不直接用乘法实现，一来节省资源，二来可提高速度！-Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!
serial_multiplex
- 绝对好东西，一个VHDL写的任意宽度通用串行乘法器，以最少的资源实现乘法器功能。-Definitely a good thing, a VHDL to write arbitrary width universal serial multiplier, the least amount of resources to achieve multiplier function.
multi
- 基于CPLD/FPGA的十六位乘法器的VHDL实现-Based on CPLD/FPGA multiplier of 16 to achieve the VHDL
Mul
- VHDL乘法器 四输入 四输出的代码设计-VHDL multiplier four input four-output code design
multi8x8
- VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier
multiplier
- 乘法器在FPGA中的VHDL代码实现教程-Multipliers in the FPGA code in VHDL Tutorial
mul24x24
- 24位x24位的乘法器 十分详细24位x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位x24位的乘法器-24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
matrix3x3
- 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
jiaotongdengsheji
- 乘法器 简单的乘法器编译 用VHDL自己编的-Compiled using a simple multiplier multiplier VHDL own series
矩阵乘法器
- 基于乘法器ip核实现的矩阵乘法器，最大支持16*16的矩阵，基于VHDL编写，仅支持整数，浮点数类型请自行添加浮点数IP核支持。