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spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
SPI_TEST
- The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave d
FPGASPI
- 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
AIC
- 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
spi_core_open
- SPI 设计 为主机设计，供大家参考,希望对大家有用-SPI master design
SPI_vrilog
- SPI接口源码,语言vrilog,包括MASTER和SLAVE-SPI interf for vrilog.
spi_master
- SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer
l1ghVhVI
- The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
SimpleCode
- SPI Master Driver with VHDL
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
xapp386
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Mas
xapp348
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner™ XPLA3 CPLD.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunne
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
simple_spi_latest.tar
- 基于vhdl的spi主从模式的程序，实现简单的SPI收发，对于实际使用学习是个比较好的例子！-VHDL SPI master-slave mode based on the procedures, the realization of a simple SPI transceiver for practical use, is a good example of learning!
spi_mem_programmer-master
- spi_mem_programmer A simple verilog module for programming (Q)SPI flash memories
verilog_spi-master
- verilog_spi A simple demo SPI interface implemented in verilog
spiVerilog-master
- spiVerilog A Verilog SPI module