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delay.rar
- 用vhdl的状态机实现精确的1us的延时程序,VHDL state machine used to achieve precise 1us delay procedures
yanshi.rar
- 给予VHDL的延时函数 是简单的开始时间的延时,VHDL delay to the start of the function is a simple time delay
LMS_filter
- verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
QuartusIIandModelSim
- 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation
lbuff_mem
- 延时代码,可以用在ＦＰＧＡ数据流水处理，图象处理，滤波-delay code
BusDelay
- buffer delay vhdl model
del_ctrl
- A VHDL logical example of memory delay controller -A VHDL logical example of memory delay controller
2
- FPGA设计中几个基本问题的分析及解决 多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the d
vhdlyanshi
- 关于vhdl语言中的延时处理，适合初学者查看，非常不错的例子，顶一下呀-With regard to the delay in vhdl language processing, suitable for beginners view, a very good example of what you Top
zdsjdt
- 自动升降电梯控制器设计 要求： 设计一个6层楼的电梯控制器。 该控制器可控制电梯完成6层楼的载客服而且遵循方向优先原则，并能响应提前关门延时关门，并具有超载报警和故障报警； 同时指示电梯运行情况和电梯内外请求信息。-Auto-Lift elevator controller design requirements: design of a six-story elevator controller. The controller can control the completio
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
delay
- 一个可以把信号拉长任意个CLk的VHDL源码例子。详见说明文档-A signal can be stretched any one CLk the VHDL source code examples. See documentation
song
- module song(clk,key,song_out,led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0] delay reg [7:0] key_reg always @(posedge clk) begin count=count+1 if((count==de
vhdl-clock-out-nodelay
- output an FPGA internal clock signal on an output port without additional routing delay
vhdl-pdelay
- programmable delay register (16-bit) in VHDL source code
ys
- 两路单极性HDB3+和HDB3-信号，经映射模块后完成单极性到双极性信号的数字转化，该模块由设计文件ys.v完成。由于映射后得到的是双极性归零码，通过该模块得到双极性非归零码。该模块由设计文件delay.v完成-Two unipolar HDB3-signals HDB3+, and by the mapping module to complete unipolar to bipolar signal digital conversion, the module completed by th
delay
- 短小易用的时序延迟程序，适用于Xilinx公司的FPGA产品-delay.vhd for Xilinx FPGA
vhdl-delay
- vhdl延时程序,源程序，已调试，可以用-VHDL delay program