搜索资源列表
dynamic_display
- 4 digital LED dynamic display的Verilog HDL源代码，它能动态的显示4位数，为FPGA 的DEBUG 提供便利，非常经典，简单易懂，并且经过了Modelsim/ISE/FPGA(XC3S250ETQ144)验证和实现，好的行为模型就应该大家分享。
nlint-user-manual nlint verilog vhdl 规则库
- nlint verilog vhdl 规则库 支持自定义 批量检查代码中bug -nlint a eda debug tool software rules ， user define rules ， verify code automatic
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
PS2
- 此代码是PS2键盘的Verilog程序，键盘的字符可显示在LCD 1602上，经上板调试程序是可行的-This code is a PS2 keyboard Verilog program, keyboard characters can be displayed on the LCD 1602, after the board debug process is feasible
jtag
- verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
uart_tx_rx
- 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complet
SDRAMController
- xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
x3cs400_uart
- 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
FPGA
- FPGA应用开发入门与典型实例 代码 FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。 -FPGA
FPGAIIC
- 用VHDL和Verilog两种语言编写的I2C总线程序！以调试通过！-VHDL and Verilog with the two languages of the I2C bus program! To debug through!
div
- VERILOG除法器，已经调试好。大家可以参照学习.-sub-divided function,I have debug it right.It is helpful to you
BEE
- 蜂鸣器实验verilog代码，我已经调试好。希望供大家学习使用。-Verilog HDL experiment code for bee. Debug it right.
moore
- moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
miaobiao
- 秒表实验verilog代码，我已经调试好。希望供大家学习使用。-clock using counter code of verilog HDL.I debug it right
LIP1501CORE_dbg_interface
- Verilog Debug interface code
ddsfinal1
- verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
Verilog
- 基于Quartus II 9.0 (32-Bit)的Verilog语言时钟程序，五个独立按键分别可调十分秒的加减和确定，此程序通过硬件调试成功。-Based on Quartus II 9.0 (32-Bit) of the Verilog language, clock, five independent second key addition and subtraction, respectively, is adjustable and determined the success of
AD9229
- AD9229 verilog调试（K7平台）-AD9229 verilog debug (K7 platform)
ARM_SOC
- ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker