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xapp622.zip
- 644 MHz SDR LVDS 发射器/接收器(verilog and doc),644-MHz SDR LVDS Transmitter/Receiver
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
Receiver
- UART Receiver Verilog Code
Receiver
- 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
RS422_receiver
- UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
Rake_Receiver
- 用Verilog HDL语言实现一个Rake接收机的最大比合并准则，其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
filter_40MHz
- 数字化中频接收机，用在AD之后的带通滤波器，VERILOG描述，32阶-Digital IF receiver, used in the AD after the bandpass filter, VERILOG descr iption, 32-step
verilog
- 这是一本介绍verilog语言的书籍，verilog语言应用于FPGA，可实现诸多实时处理模块，例如实时OFDM发射机和接收机的制作-verilog for FPGA，real time OFDM Transmitter and receiver
Verilog-Code-Receiver
- Verilog Code for Receiver USART
RECEIVER
- 此程序为基于OFDM的802.11a的接收端的VERILOG代码，包含所有模块。-This program is VERILOG code receiving end 802.11a OFDM-based, including all modules.
遥控器接收解码电路
- 设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
Receiver_spartn6_v1
- Implement design of UART receiver in verilog
UartRecv
- 利用FPGA实现简单的串口接收驱动程序，actel。(Using FPGA to implement a simple serial port receiver driver, Actel)
Verilog
- aes digital audio interface from xilinx
xapp495(1)
- 实现HDMI的receiver和transmitter，来源xilinx xapp(Implement HDMI interface 1.0, including receiver and transmitter,from Xilinx xapp)
rx_module
- 接收机的顶层模块构建,对需要参考的朋友有一定的帮助(The construction of the top module of the receiver is helpful to friends who need reference.)
好-无线通信FPGA设计-Xilinx
- 《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless