搜索资源列表
Verilog
- 异步fifo的经典写法，使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计，供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
miniuart.tar
- Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost eve
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
Vector_Variable_Frequency_System_Based_on_TMS320F
- This paper analyzes the vector control theory of asynchronous motors based on the magnetic orientation of motor rotors, and its mathematical model is made. Then the variable frequency vector speed-adjusting experimental system is built with the DSP T
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
aFifo
- This an implementation of an Asynchronous FIFO written in Verilog 2001.-This is an implementation of an Asynchronous FIFO written in Verilog 2001.
asynfifo
- 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
experiment4_play
- VHDL实验四，设计一个异步清零和同步时钟使能的4位加法计数器-VHDL Experiment 4, an asynchronous reset and synchronous design clock enable 4-bit adder counter
fifo
- Asynchronous FIFO source code
1840315
- 电机学课件，共7章。包括：单相变压器的空载运行、变压器参数测定、变标么值及运行特性、电磁转矩和转矩特性、三相异步电动机的电力拖动、同步发电机电枢反应、同发方程式相量图、同步发电机的并联运行、直流发电机与直流电动机的区别、直流电动机的电驱电动势和电磁转矩等。 -Motor learning courseware, a total of 7 chapters. Including: single-phase transformer no-load operation, transformers
aFifo
- 很好用的异步FIFO设计代码，和大家共享一下，这是我在一个美国的网站上找到的-Asynchronous FIFO design with good code, and share how this is an American site I found on
Asynchronous-FIFO-design
- 异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full independence, thus data loss pro
Asynchronous-serial-communication
- 用于MSP430F149。 异步通讯。 从串口接收数据，分析收到的数据包，然后根据算法进行运算，最后 将结果从串口返回-For MSP430F149. Asynchronous communication. From the serial port to receive data, analyze the data packets received, then the algorithm operation, the final results back from the se
Flag-of-asynchronous-FIFO
- Quartus平台，VHDL代码编写的带标志位的异步FIFO。-Quartus platform, VHDL code is written with the sign bit of the asynchronous FIFO.
asynchronous-clock-boundary
- 一个关于跨越异步时钟边界传输数据的解决方案-The solution of transfering data across asynchronous clock boundary.
Asynchronous FIFO Architectures
- 老外的经典异步FIFO结构讲解，一共三个部分。(Asynchronous FIFO Architectures Vijay A. Nebhrajani)