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aduc7000_pwm
- This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 an
Z1602
- KS0070(44780) 16x2 字符液晶屏驱动演示程序总线方式。 连接线图: DB0--P0.0 DB4--P0.4 RW--P2.0 DB1--P0.1 DB5--P0.5 RC--P2.1 DB2--P0.2 DB6--P0.6 E--P2.7 =>74ls00+wr+rd DB3--P0.3 DB7--P0.7 VLCD接1K2电阻到GND [注]:AT89C51的晶振频率为12MHz-KS0070 (44,780) 16x2
PPT_timing-constraint
- PPT的形式演示Xilinx-ISE环境下时序约束的实现个结果
timing_constraint
- 主要介绍xilinxFPGA时序约束的方法和技巧。FPGA开发人员进一步提高的必看资料。-XilinxFPGA timing constraints introduces methods and techniques. FPGA developers to further enhance the information of the must-see.
HardwareDesignandImplementationforaPRCardBasedonTI
- 在交通收费和路口监控等车牌识别应用中,纯粹依靠PC机通常难以达到实时性,应用受到了限制, 在将DSP引入到车牌识别应用系统后,此问题可得到较好解决。本DSP系统以TIC6201 DSP处理器为核心,配置 SAA7111A视频解码芯片SAA7111A作为图像输入通道,使用PCI2040实现了DSP以PCI接口方式与PC的通信。 在此系统中,DSP运行识别算法,然后将识别结果通过PCI接口传输给PC供PC进行显示和管理。整个系统计算 分布合理,实时性强,极大提高了实用性 -The
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
Constraint-Based-Verification
- 系統化驗証方法及實例探討Assertion, Constraint synthesis-Electronic Design complexity getting higher, the verification work needs to be fully understood
yuping
- 分析了噪声背景下实谐波过程ARMA模型系数之间的对称性,并以此为约束条件加入ARMA谱估计方法的求解过程中,从而提出了一种改进的正弦信号频率估计方法.理论分析与计算机仿真表明,对于低信噪比条件下的正弦信号参量估计,这一算法的精度与稳定性都优于仅使用总体最小二乘法(SVD-TLS)的ARMA谱估计方法.-Analysis of real harmonic process noise background symmetry between ARMA model coefficients, and a
ViterbiFPGA
- 探讨了CDMA 数字移动通信中的差错控制问题, 研究用约束度K = 9 的卷积编码 和最大似然V iterbi 译码的差错控制方案. 在V iterbi 译码算法中, 提出了原位运算度量、保 存路径转移过程和循环存取幸存路径等方法, 能有效地减少存储量、降低功耗, 使得K = 9 的V iterbi 译码算法可在以单片XC4010 FPGA 为主的器件上实现, 其性能指标符合CD2 MA 数字移动通信IS 95 标准要求. 文中给出了实测的算法性能, 讨论了FPGA 具体实现
10.1.1.120.9181
- Priority based dynamic spectrum access with QoS and interference temperature constraint》.郑海涛的论文，认知无线电频谱管理分配研究，大牛哦-Priority based dynamic spectrum access with QoS and interference temperature constraint " . Haitao papers, radio spectrum management
top_PR
- 用户将使用具有局部重配置能力的ISE 12.1，进行综合HDL模块并完成设计。之后，使用PlanAhead12.1来布局规划设计，并内部调用执行和分析工具，包括：调用FPGA Editor查看设计实现 调用Constraint Editor创建时序约束；用Timing Analyzer进行时序分析。最后，用户可以用XUPV5开发板来进行硬件验证，并用iMPACT软件来下载全局和局部比特流。-Top-level design dynamically reconfigurable, static l
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
hibernate_validator
- Hibernate Validator Reference Guide Hibernate Validator works at two levels. First, it is able to check in-memory instances of a class for constraint violations. Second, it can apply the constraints to the Hibernate metamodel and incorporate
zjw
- XILINX ise上成功实现源文件、仿真文件、约束文件的编写，经验证正确无误-XILINX ise on the successful implementation of the source files, simulation files, the constraint file preparation, proven correct
viterbi-deoder
- viterbi decoder with constraint length 7,4
Xilinx-Timing
- Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由-Xilinx FPGA timing constraint information, original, classic no reason
ml605_MIG_rdf0011_13.4_c
- 该参考程序是基于xilinx ml605开发板的一个DDR3参考设计，源文件包含相应的管脚约束文件。-The reference procedure is based on xilinx ml605 development board a DDR3 reference design source file contains the corresponding pin constraint file.
SSRAM_250M
- 本人编写的SSRAM高速读写工程，工程中包含了NIOS软核，利用Quartus的TimeQuest工具进行了时序约束，上班调试最高读写速率可达250MHz。-I write the SSRAM high-speed, speaking, reading and writing, engineering includes NIOS soft core, timing constraint is studied by using Quartus TimeQuest tools, work to de
mcu-cpld-c
- 单片机与CPLD通信的端口约束代码，保证单片机与CPLD的通信-Port constraint code to communicate with the MCU CPLD ensure MCU and CPLD communication
IO-timing-constrain-in-fpga
- 对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules