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Generate trellis data of a rate-1/n convolutional encoder.卷积码1/n的编码器，注意生成的是非系统码。-Generate trellis data of a rate-1/n convolutional encoder. Convolutional codes 1/n of the encoder, the attention generated by the non-system code.
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卷积编码的有关介绍，有关论文，以及有关matlab程序代码-Convolutional code introduced the paper, as well as the Matlab code
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(2,1,3)卷积码编码，硬判决译码；编码是matlab语言，译码是verilog语言-(2,1,3) convolutional code encoding, hard decision decoding coding is matlab language, decoding is verilog language
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(2,1,3)卷积码编码，软判决译码；matlab语言编码；verilog语言译码；-(2,1,3) convolutional code encoding, soft-decision decoding matlab coding verilog decoder
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本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
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