搜索资源列表
filter1300
- 用于TM1300/PNX1300系列DSP（主要用于视频处理）的各种滤波器源码，包括fir/iir,以及dct和idct等。-for TM1300/PNX1300 Series DSP (mainly for video processing), the filter All source code, including fir / IIR, and A1501 and IDCT so.
20060412183015974
- 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
dct.rar
- 离散余弦变换的设计源代码以及测试源代码和仿真图,Design of discrete cosine transform source code and test source code and simulation plan
two_d_dct_serial
- Verilog codes for 2D Discrete Cosine Transform (DCT)
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
dct-code
- 离散余弦变换的VHDL实现，不错的代码和方法-Discrete cosine transform VHDL realization of good code and methods
DCT
- ARM汇编，实现DCT算法，图像压缩，JPEG 需要loadmemory，里面附带load文件示例以及样子图片，raw格式-ARM compilation and realizing DCT algorithm, image compression, JPEG need loadmemory, incidental load inside sample documents, as well as look like picture, raw format
main_dct
- verilog code for dct
xapp610
- Verilog code for 2D-DCT with detailed documentation.
1DCT_VHDL
- VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation
verilogdct
- dct实现verilog hdl的数字图像处理，源代码-dct achieve verilog hdl digital image processing, source code
attachments_2010_01_29
- dct and idct vhdl code
ModelSim
- verilog Source code for DCT
DCT_IDCT
- verilog code for DCT and IDCT (JPEG)
LIP6911CORE_dct_4
- DCT Verilog source code
DCT2
- 2 维 DCT的VHDL实现以及 测试代码 ， -2-D DCT of the VHDL implementation and test code
dct-partial-code
- this is VHDL code for dct initialization
DCT
- Discrete Cosine transform VHDL code, with a positive transformation within the inverse transform of the test file.
DCT
- Discrete Cosign Transform(DCT) Verilog Source Code
verilog dct
- 其使用模块的代码风格来编写，能够8点dct的转换(Its use of the module's code style to write, to 8 dct conversion)