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  1. equlizer

    0下载:
  2. 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integra
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:23.17kb
    • 提供者:陈为
  1. DLMS

    0下载:
  2. DLMS equalizer for qam
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:3.3kb
    • 提供者:cyberia
  1. band_equalization

    0下载:
  2. AMIS單晶片開發範本,等化器使用bs250晶片,基本dsp編程。-AMIS to develop single-chip model, the chip equalizer use bs250, basic dsp programming.
  3. 所属分类:DSP program

    • 发布日期:2017-04-27
    • 文件大小:18.79kb
    • 提供者:ming
  1. adaptive_lms_equalizer_latest.tar

    0下载:
  2. In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:13.54kb
    • 提供者:Arun
  1. fir_9222_sopc

    0下载:
  2. 基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-20
    • 文件大小:5.64mb
    • 提供者:z
  1. IterativeDecodingofBinary

    0下载:
  2. In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1.45mb
    • 提供者:suresh
  1. RECURSIVEALGORITHMFOREFFICIENTMAPDECODING

    0下载:
  2. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:101.84kb
    • 提供者:suresh
  1. VerilogLangRefManual

    0下载:
  2. Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1.22mb
    • 提供者:suresh
  1. shuzifupingjunheng

    0下载:
  2. 以DSP F2812为开发平台的数字幅频均衡器,可补偿音频范围内的波形。-To DSP F2812 digital platform for the development of amplitude-frequency equalizer, to compensate the waveform within the audio range.
  3. 所属分类:DSP program

    • 发布日期:2017-04-06
    • 文件大小:2.92kb
    • 提供者:AJ
  1. junhengqi

    1下载:
  2. 数字信号处理均衡器,具有普遍实用性,带通低通和高通共同实现-Digital Signal Processing Equalizer
  3. 所属分类:DSP program

    • 发布日期:2017-03-31
    • 文件大小:1.69kb
    • 提供者:ip
  1. 5_band_graphic_equalizer

    0下载:
  2. 5_band graphic equalizer circuit using a single IC-chip
  3. 所属分类:Embeded-SCM Develop

    • 发布日期:2017-04-07
    • 文件大小:33kb
    • 提供者:mhyus
  1. main

    0下载:
  2. 数值均衡器,可以通过手动调节分频点,通过LCD屏显示分频状态-The main program, equalizer DaBing LCD display, can play the role, the frequency hopping manual revision points
  3. 所属分类:SCM

    • 发布日期:2017-04-08
    • 文件大小:2.85kb
    • 提供者:hs
  1. GraphicEqualizer

    0下载:
  2. Graphic Equalizer sample display -Graphic Equalizer sample display
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:582.02kb
    • 提供者:zhang
  1. impfse

    0下载:
  2. this helps us to understand and enhance the knowledge on fractionally spaced equalizer of constant modulus algorithm
  3. 所属分类:SCM

    • 发布日期:2017-05-02
    • 文件大小:774.04kb
    • 提供者:kalyan
  1. QAM16_demo

    0下载:
  2. This a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery. -This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xil
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:43.52kb
    • 提供者:徐滨
  1. Eqalizer_filter_iir

    0下载:
  2. 采用visual dsp实现网络均衡器,采用IIR滤波器方法实现-Achieved by visual dsp equalizer network, using IIR filter method implementation
  3. 所属分类:DSP program

    • 发布日期:2017-04-08
    • 文件大小:163.13kb
    • 提供者:liang
  1. Battery-equalizer-code

    0下载:
  2. 电池均衡器代码,实现4节电池自均衡。包括自动、手动均衡模式。附带注释。-Battery equalizer code
  3. 所属分类:SCM

    • 发布日期:2017-11-30
    • 文件大小:50.83kb
    • 提供者:王者
  1. Equalizer-master

    0下载:
  2. equalizer application for android
  3. 所属分类:Other Embeded program

    • 发布日期:2017-04-17
    • 文件大小:81.77kb
    • 提供者:edmond.yun
  1. equalizer

    0下载:
  2. This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1.23kb
    • 提供者:rion
  1. equalizer

    0下载:
  2. matlab code for ZF equalizer
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-09
    • 文件大小:1kb
    • 提供者:MJSO
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