In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco

频率计，通过单片机 CPLD共同实现对输入方波信号测频率，测量范围1—10Mhz，带数码管译码显示-Frequency counter, through the joint realization of single chip CPLD input square wave signal measured on the frequency, measurement range 1-10Mhz, with a digital display control decoding

PS2的键盘解码和led灯显示解码的联合，适合初学者，VHDL程序-PS2 keyboard decoding and joint decoding led light display, suitable for beginners, VHDL program