1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)

LBS基站定位，使用STM32和GC65模块采集经纬度，通过短信形式发送-LBS STM32 GC65 SMS Test OK！

nordic nrf51 低功耗蓝牙开发参考代码。-nordic bluetooth sample